Embodiments of the inventive subject matter generally relate to the field of computers, and, more particularly, to reducing microprocessor performance loss due to translation table coherency in a multi-processor system.
Multi-processor (MP) coherency protocols in a MP system ensure that all processors use up-to-date data from caches and translation tables (e.g., a translation lookaside buffer (TLB)). When an operating system updates a translation table, all processors in the MP system are notified to handle the change by a TLB MP-coherency operation (hereinafter “MP-coherency operation”). For example, processors are drained and purge affected entries from TLBs (i.e., all instruction queues in the processors are drained) and no instructions must be executed in order to perform the purge. After the purge a processor can answer the MP-coherency operation. When all processors have answered the MP-coherency operation, a modified table entry(ies) is written and all processors are allowed to continue executing instructions. Performance improvements to this technique include a zone (also known as Logical Partition) filtering technique. A zone has its own storage assigned to it which is disjunct to storage assigned to other zones. MP-coherency operations originating from a particular zone do not need to interrupt or drain processors running in a different zone because no storage access of instructions in flight can possibly collide with the purge operation. Only a TLB level(s) that may still hold entries from the originating zone need to be purged. However, processors running in the same zone as the originator must still be interrupted and remain drained until the MP-coherency operation is finished. In another improvement, each processor in the same zone is drained individually. On purge of the processor's own TLB and answering the MP-coherency operation, each processor may continue to execute instructions as long as it does not access the affected storage locations or translation tables. If the processor finds accesses to the affected storage locations or translation tables, the processor waits until it receives a signal that the MP-coherency operation is finished. However, the processors in the MP system still suffer a performance penalty as they are interrupted and drained.